HD155121F Datasheet, PDF (52/57 Pages) Hitachi Semiconductor – RF Transceiver IC for GSM and PCN Dual band cellular systems

HD155121F
Appendix A
Transmitter Architecture (offset PLL architecture)
The HD155121F generates a modulated signal at IF with a quadrature modulator and converts it to a final
frequency with an Offset Phase Locked Loop (OPLL).
The Offset Phase Locked Loop is simply a PLL with a down conversion mixer in the feedback path.
Using a down converter in the feed back path acts as an up converter in the forward path, which allows the
output frequency to be different from the comparison frequency without affecting the normal operation of
the loop. Phase / frequency changes in the reference signal are not scaled, as they would be if a divider
were used in the feed back path, and hence the modulation is faithfully reproduced at the final frequency.
The main advantage of the OPLL in this application is that it forms a tracking band pass filter around the
modulated signal. This is because the loop cannot respond to phase variations at the reference that are
outside its closed loop bandwidth. Thus the broad band phase noise from the quadrature modulator is
shaped by the frequency response of the closed loop allowing the TX noise specifications to be met without
further filtering.
A secondary advantage of the OPLL is that the output signal, coming from a VCO, is truly constant
envelope. This removes the problem of spectral spreading caused by AM to AM and AM to PM
conversion in the power amplifier.
The OPLL is formed from an on-chip Gilbert cell down converter, limitters and phase detector with an off-
chip passive loop filter and VCO. The phase detector is implemented as a Gilbert cell with a current source
output stage, which allows an integrator to be included in the passive loop filter. This is similar to the
technique commonly used in PLL synthesizers.
As is well known, when out of lock, a mixer type phase detector does not provide any frequency
discrimination. This means that the under normal circumstances, a loop of this type is not guaranteed to
lock. However in the HD155121F, a well defined offset current is added to the phase detector output, so
that when the loop is out of lock, this offset current linearly charges the capacitors in the loop filter. This
has the effect of sweeping the VCO across the band. When the down converted signal from the VCO
approaches the reference frequency, the Gilbert cell begins to operate as a phase detector and the loop
acquires in the normal way. The presence of the offset current in lock is unimportant, as it only results in a
static phase offset between the final signal and the reference signal.
At the end of the transmit burst, when the transmitter is disabled, a switch closes to discharge the loop filter
capacitors. This resets the acquisition process in preparation for the start of the next burst.
The closed loop bandwidth of the OPLL should be designed to be around 1.2 to 1.5 MHz, which should be
large enough to allow rapid locking and accurate tracking of the modulation. If the bandwidth is too large,
the OPLL will not reject the noise from the modulator sufficiently. The ideal bandwidth will be a
compromise dependant on the noise performance of the VCO and amplifier chain.
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