HN29W12811 Datasheet, PDF (20/42 Pages) Hitachi Semiconductor – 128M AND type Flash Memory More than 8,029-sector (135,657,984-bit)

HN29W12811 Series
HN29W12811
-60
Parameter
Symbol Min Typ Max Unit Test conditions
Notes
RES high to device ready
t _BSY
——1
ms
CE pulse high time
t _CPH
200 — — ns
CE, WE setup time for RES
t _CWRS
0
— — ns
RES to CE, WE hold time
t _CWRH
0
— — ns
SC setup for WE
t _SW
50 — — ns
CE hold time for OE
t _COH
0
— — ns
SA (2) to CA (2) delay time
t _SCD
— — 30 µs
RDY/Busy setup for SC
t _RS
200 — — ns
Time to device busy on read mode t_DBR
——1
µs
Busy time on reset mode
t _RBSY
— 45 — µs
Notes: 1. t_DF is a time after which the I/O pins become open.
2. t_WSD (min) is specified as a reference point only for SC, if t_WSD is greater than the specified t_WSD (min)
limit, then access time is controlled exclusively by t_SAC.
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