HMP8112 Datasheet, PDF (8/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
phase alternates from line to line by 90^o. To fully separate
the PAL chrominance and luminance signals the user select-
able filters should be enabled. The chroma notch filter built
into the luminance channel should be enabled for PAL sys-
tems to reduce cross luminance effects. The low pass filter
in the chrominance processing chain helps to reduce cross
color products.
pin. This signal follows the horizontal sync of an input video
source. If there is no source the HSYNC pin will continue to
run at video rates due to the Line Locked PLL free-running.
HSYNC can be moved throughout the video line using the
HSYNC Start and End time registers. This 10-bit register
allows the HSYNC to be moved in OSR clock increments
(12.27MHZ, 13.5MHz or 14.75MHz).
AMPLITUDE
Y _{I, Q}
I, Q
Y
AMPLITUDE
f_H/4
f_H/4
f_H
FREQUENCY
Y
I, Q
I, Q
Y
FREQUENCY
FIGURE 5. COMPOSITE PAL INTERLEAVE SCHEME
The demodulator in the decoder decodes the color compo-
nents into U and V. The U and V components are converted
to Cb and Cr components after the decoding process.
YCbCr has a usable data range as shown in Figure 4. The
data range for Y is limited to a minimum of 16.
255
255
255
248
WHITE ₂₄₀
BLUE
240
RED
100%
100%
100%
212
BLUE
212
75%
RED
75%
128
128
128
16
BLACK
Y DATA
RANGE
44
YELLOW
75%
YELLOW
16
100%
0
Cb DATA
RANGE
44
CYAN
75%
CYAN
16
100%
0
Cr DATA
RANGE
FIGURE 6. YCbCr DATA RANGES
The decoder is compatible with all NTSC and PAL video for-
mats available throughout the world. Table 2 shows the com-
patible video standards.
Horizontal Sync Detection
Horizontal sync is detected in the Output Sample Rate con-
verter (OSR). The OSR spatially aligns the pixels in the verti-
cal direction by using the horizontal sync information
embedded in the digital video data stream. The HSYNC
sync pulse out of the decoder is a video synchronous output
Vertical Sync And Field Detection
The vertical sync and field detect circuit of the decoder uses
a low time counter to detect the vertical sync sequence in
the video data stream. The low time counter accumulates
the low time encounted after the horizontal sync edge or at
the start of each line. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted
immediately. VSYNC will remain asserted for a minimum of 1
line. The FIELD flag is updated at the same time as the
VSYNC line. The FIELD pin is a ‘0’ for ODD fields and a ‘1’
for even fields.
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD flag will
continue to toggle. Lost vertical sync is declared if after 337
lines a vertical sync period was not detected for 3 succes-
sive lines. When this occurs the phase locked loops are ini-
tialized to the acquisition state.
The VSYNC pulse out of the decoder follows the vertical
sync detection and is typically 6.5 lines long. The VSYNC
will run at the field rate of the selected video standard
selected. For NTSC the field rate is 60Hz and for PAL the
field rate is 50Hz. This signal will continue to run even in the
event of no incoming video signal.
Internal Phase Locked Loops
The HMP8112 has two independent digital phase locked
loops on chip. A chroma phase-locked loop is implemented
to maintain chroma lock for demodulation of the color chan-
nel, and a line locked phase lock loop is implemented to
maintain vertical spatial alignment. The phase locked loops
are designed to maintain lock even in the event of VCR
headswitches and multipath noise.
The HMP8112 can use a main crystal (CLK) of 20MHz to
30MHz. The crystal is used as a reference frequency for the
internal phase locked loops. The ratio of the crystal fre-
quency to the video standard is programmed into an internal
register for the PLLs to correctly decode video.
The HMP8112 decoder contains 2 sample rate converters
and 2 phase locked loops that lock to the incoming video. The
input sample rate converter synchronizes the digitized video
from the CLK rate to a 4xf_SC rate. The chrominance is sepa-
rated from the luminance and then demodulated. The Chroma
phase locked loop uses the CLK source as the PLL reference
frequency. To initialize the chroma PLL, the CLK to 4xf_SC ratio
must be loaded. For example, if the CLK was 27MHz and the
video signal is NTSC (4 x 3.579545MHz = 14.318MHz) then
the ratio loaded is 0.5302895 in 16-bit precision.
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