HMP8112 Datasheet, PDF (13/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
Reset
The RESET pin is used to return the decoder to an initializa-
tion state. This pin should be used after a power-up to set
the part into a known state. The internal registers are
returned to their RESET state and the Serial I²C port is
returned to inactive state. The RESET pin is an active low
signal and should be asserted for minimum of 1 CLK cycle.
After a RESET or a software reset has occurred all output
pins are three-stated. The following pins must be pulled high
to ensure proper operation:
HSYNC
VSYNC
DVLD
ACTIVE
FIELD
A 10K or smaller pullup resistor to V_CC is recommended.
CLK
t_DLY
DVLD
ACTIVE
NOTE 2
Y[7-0]
Y_N
Y₀
Y₁
Y₂
t_DVLD
NOTE 1
CbCr[7-0]
Cr_N
Cb₀
Cr₀
Cb₁
NOTES:
1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
due to the 4:2:2 subsampling.
2. Active is asserted for lines 22-262.5 and 285.5-525. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD
is asserted during vertical and horizontal sync.
FIGURE 15A. OUTPUT TIMING 16-BIT MODE
/
NTSC M, N PAL M
LINES 1-21
<- PIXEL 0
LINES 22-263.5
(PAL B, D, G, H, I, N COMB N)
(LINES 1-23.5)
(LINES 23.5-310)
NTSC M, N PAL M
LINES 263.5-284
(PAL B, D, G, H, I, N COMB N)
(LINES 311-335)
<- PIXEL 0
LINES 285-525
(LINES 336-623.5)
CLK
DVLDY
ACTIVE
Y[7-0]
FIGURE 15B. ACTIVE VIDEO REGIONS IN 16-BIT MODE
t_DLY
PIXEL 1 PIXEL 2 PIXEL 3 PIXEL N-3 PIXEL N-2 PIXEL N-1 PIXEL N
t_DVLD
Cb₀
Y₀
Cr₀
Y₁
Cb₂
Y₂
Cr₂
FIGURE 16. OUTPUT TIMING 8-BIT MODE
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