HMP8112 Datasheet, PDF (12/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
CLK frequency and Table 5 shows the number of data points
per video line to expect for a given standard. Data is output as
4:2:2 subsampled data in a Y-Cb/Y-Cr 16-bit sequence. The
Data Valid (DVLD) flag is asserted when video data is present
on the 16-bit output port of the HMP8112 (Y[7:0], CbCr[7:0]).
The ACTIVE flag is asserted when the active video portion of
the horizontal scan line is present on the data output port. See
Figure 15 for Synchronous Pixel Transfer Mode timing. DVLD is
asserted every time the output sample rate converter has a
valid output. When DVLD and ACTIVE are used together the
visual portion of the image can be captured. When DVLD is
used alone all valid data during the Horizontal, Vertical and Ref-
erence Burst Timing are available. ACTIVE is asserted from
lines 22 through 262.5 and lines 285.5 through 525 for NTSC
(and PAL M). Active is asserted from lines 23.5 through 310
and lines 336 through 623.5 for PAL (B, D, G, H, I, N, Comb N).
The CLK can be run on a 20MHz - 30MHz clock source. Data
will be output (on average) at the Output Data Rate shown in
Table 5 for a given standard. Data is clocked out synchronous
to CLK and will come in bursts. To smooth out the data rate to
a regular rate a CLK of 2X the average output data rate can
be used. In the 16-bit pixel transfer, data is sequenced on the
CbCr[7:0] data bus, starting with Cb and then Cr.
TABLE 5. OUTPUT MODE STANDARDS
STANDARD
OUTPUT ACTIVE TOTAL
DATA PIXELS/ PIXELS/
RATE LINE
LINE
TOTAL
LINES/
FIELD
NTSC Square Pixel 12.27MHz 640
780
262.5
NTSC CCIR 601
13.5MHz 720
858
262.5
PAL B, D, G, H, I, N, 13.5MHz 720
COMB N, CCIR601
864
312.5
PAL M CCIR 601 13.5MHz 720
858
262.5
PAL B, D, G, H, I, N 14.74MHz 768
Square Pixel
944
312.5
PAL M Square Pixel 14.74MHz 640
780
312.5
For Burst Mode output format the Y[7:0] output bus is used
to transfer all YCbCr data in 8-bit format. The data is also
4:2:2 subsampled but will only contain the active video por-
tion of the line. The HMP8112 uses an internal 32 deep fifo
to handle latencies between the output sample rate and the
CLK frequency. In this mode, the data is clocked out at the
CLK rate and only clock frequencies of 24.5454MHz, 27MHz
and 29.5MHz can be used. In 8-bit data mode, the data is
sequenced on the Y[7:0] bus in Cb, Y, Cr, Y format. ACTIVE
is asserted as soon as the mode is selected. DVLD when
asserted indicates a valid active pixel is available. Pixels dur-
ing the horizontal and vertical blanking are not available.
Only the active portions of the video line are output.
SDA
SCL
S
1-7
8
9
1-7
8
START
CONDITION
ADDRESS
R/W
ACK
DATA
FIGURE 13. I²C SERIAL TIMING FLOW
9
ACK
P
STOP
CONDITION
DATA WRITE _{1000 100 (R/W)}
S CHIP ADDR A
SUB ADDR
0x88
DATA READ _{1000 100 (R/W)}
S CHIP ADDR A
SUB ADDR
0x88
A DATA A
REGISTER
POINTED
TO BY
SUBADDR
DATA
AP
AS
CHIP ADDR
0x89
A DATA
A
REGISTER
POINTED
TO BY
SUBADDR
DATA
NA P
FIGURE 14. REGISTER WRITE PROGRAMMING FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FROM MASTER
FROM HMP8112
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