HMP8112 Datasheet, PDF (18/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
TABLE 20. HORIZONTAL SYNC END TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 0E_H
DESCRIPTION
RESET
STATE
7-0
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
0010 0000_B
TABLE 21. HORIZONTAL SYNC END TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 0F_H
DESCRIPTION
15 - 10 Not Used
Write Ignored, Read 0’s
9-8
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
RESET
STATE
XXXX XX
00_B
TABLE 22. PHASE LOCKED LOOP ADJUST REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 10_H
DESCRIPTION
RESET
STATE
7-0
Phase Locked Loop The Phase Locked Loop time constants can be changed for testing purposes. It is rec-
Filter Adjust Test
Register
ommended that the default value of (20_H) always be used. The reset state is 00_H.
0000 0000_B
TABLE 23. PHASE LOCKED LOOP SYNC DETECT WINDOW REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 11_H
DESCRIPTION
RESET
STATE
7-0
Phase Locked Loop
Horizontal Sync
Detect Window
These bits control the PLL horizontal sync detect window. This window sets the length
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs. For NTSC this value should be DD_H and for PAL, FF_H.
1101 1101_B
TABLE 24. DC RESTORE START TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 12_H
DESCRIPTION
RESET
STATE
7-0
DC Restore
This register provides a programmable delay for the internal DC RES signal. The start
Programmable Start time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
0011 0111_B
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