HMP8112 Datasheet, PDF (19/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
TABLE 25. DC RESTORE START TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 13_H
DESCRIPTION
15 - 10 Not Used
9-8
DC Restore
This register provides a programmable delay for the internal DC RES signal. The start
Programmable Start time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
RESET
STATE
XXXX XX
00_B
TABLE 26. DC RESTORE END TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 14_H
DESCRIPTION
RESET
STATE
7-0
DC Restore
Programmable End
Time
This register provides a programmable delay for the internal DC RES signal. The end
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
0101 0010_B
TABLE 27. DC RESTORE END TIME REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 15_H
DESCRIPTION
15 - 10 Not Used
9-8
DC Restore
Programmable End
Time
This register provides a programmable delay for the external DC RES signal. The end
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
RESET
STATE
XXXX XX
00_B
TABLE 28. OUTPUT FORMAT CONTROL REGISTER
BIT
NUMBER
FUNCTION
DESTINATION ADDRESS = 16_H
DESCRIPTION
7
Square Pixel/ITU-R When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.
BT601 Select
6, 5, 4
Output Field Control These bits control the field capture rate of the HMP8112. The user can select every 4th
“FLD_CONT(2-0)” field, every other field or every field of video to be output to the data port.
000 = No Capture Enabled
001 = Capture every 4th field
010 = Capture every 2nd field
011 = Capture every 2nd odd field
100 = Capture every 2nd even field
101 = Capture every odd field
110 = Capture every even field
111 = Capture all fields
3
8/16 output Select When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-
nous Pixel Transfer output mode is selected.
2
OEN
This bit enables the Y(7-0), CbCr(7-0), ACTIVE, HSYNC, VSYNC and DVLD outputs.
1 = Outputs enabled; 0 = three-stated.
RESET
STATE
0_B
000_B
0_B
0_B
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