HMP8112 Datasheet, PDF (23/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
Pin Description (Continued)
NAME
PQFP PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
VSYNC
70
Output Vertical Sync. This video synchronous pulse is generated by the detection of a vertical
sync on the video input. In the absence of video the VSYNC rate is set by the over flow
of the internal line rate counter. This pin is three-stated after a RESET or software reset
and should be pulled high through a 10K resistor.
FIELD
67
Output Field Flag. When set (‘0’) this signals that an ODD field is presently being output from
the decoder. When cleared (‘1’) this signals an EVEN field. This flag will toggle when
no vertical sync is detected and 337 lines have elapsed. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
ACTIVE
65
Output Active Video Flag. This flag is asserted (‘1’) when the active portion of the video line
is available on the output port. This signal is always set during Burst Output data
mode. This flag is free running and synchronous to CLK. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
TEST
36
Input Test input. This pin is used for production test and should be connected to digital
ground.
DV_CC
26, 31,37, 44,
52, 59, 68, 75,
79
Input 5V Logic Supply Pins
DGND
25, 32, 33, 35,
39, 46, 53, 61,
62, 69, 72, 73,
80
Input Digital Ground Pins
AV_CC
AGND
2, 12,14
1, 3, 10, 11,
15,16, 21, 22,
23, 24
Input
Input
5V Analog Supply Pins
Analog GND
A/D TEST
17
Output A/D Test Pin. This pin should be left open.
NC
4, 18, 20, 74
NA
No Connect. These pins should be left open.
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