HMP8112 Datasheet, PDF (22/40 Pages) Harris Corporation – NTSC/PAL Video Decoder

HMP8112
Pin Description
NAME
LIN[0:2]
CIN
WPE
GAIN_CTRL
DEC_T
DEC_L
LAGC_CAP
LCLAMP_CAP
CCLAMP_CAP
L_ADIN
L_OUT
SDA
SCL
CLK
RESET
CbCr[0:7]
Y[0:7]
DVLD
HSYNC
PQFP PIN
NUMBER
5, 6, 7
19
27
28
78
30
77
76
29
8
9
40
41
13, 38
34
42, 43, 45,
47-51
54-58, 60, 63,
64
66
71
INPUT/
OUTPUT
DESCRIPTION
Input
Analog Video Inputs. Inputs 0 and 1 are composite inputs. Input 2 can be either a
composite input or the Y component of an S-Video signal.
Input Analog Chroma input component of an S-Video Input.
Input
White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when
the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip
when the A/D reaches code 255.
Input Gain Control Input. DC voltage to set the video amplifier’s gain.
Input
Decoupling for A/D Converter Reference. Connect a 0.01µF and 0.1µF capacitors to
AGND.
Input
Decoupling for A/D Converter Reference. Connect a 0.01µF and 0.1µF capacitors to
AGND.
Input
Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time con-
stant.
Input
Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time
constant.
Input
Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time
constant.
Input Luminance A/D Converters input from antialiasing filter.
Output
Input/
Output
Input
Luminance or Composite Analog Video Amplifier output to antialiasing filter.
The serial I²C serial input/output data line.
The serial I²C serial bus clock line.
Input
Master clock for the decoder. This clock is used to run the internal logic, A/D convert-
ers, and Phase Locked Loops. All I/O pins (except the I²C) are synchronous to this
master clock. A 50ppmcrystal should be used with a waveform symmetry of 60/40%
or better.
Input
Asynchronous Reset pin. Master Chip reset to initialize the internal states and set
the internal registers to a known state.
Output
CbCr Data Output Port. The chrominance data output port of the decoder. Data is in
unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2
format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the
first sample of a line always being Cb. The port is designed to minimize external logic
needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Output
Y Data Output Port. The luminance data output port of the decoder. Data is in un-
signed format and can range from 16 to 255. The port is designed to minimize exter-
nal logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Output
Data Valid. This pin signals when valid data is available on the data output ports. This
pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
Output
Horizontal Sync. This video synchronous pulse is generated by the detection of hor-
izontal sync on the video input. In the absence of video, the HSYNC rate is set when
the internal PLL counters overflow. The HSYNC begin and end time can be pro-
grammed and is synchronous to CLK. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
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