GS8182S18D Datasheet, PDF (9/31 Pages) GSI Technology – 18Mb Burst of 2 DDR SigmaSIO-II SRAM

GS8182S18D-267/250/200/167
Separate I/O Burst of 2 SigmaSIO-II SRAM Truth Table
A LD R/W
Current
Operation
D
D
Q
Q
K↑ K↑ K↑
(t_n) (t_n) (t_n)
X
1
X
K↑
(t_n)
Deselect
K↑
(t_n+1)
X
K↑
(t_n+1)
—
K↑
(t_n+1)
Hi-Z
K↑
(t_n+1)
—
V
0
1
Read
X
—
Q0
Q1
V
0
0
Write
D0
D1
Hi-Z
—
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
Rev: 1.08a 8/2005
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology