GS8182S18D Datasheet, PDF (4/31 Pages) GSI Technology – 18Mb Burst of 2 DDR SigmaSIO-II SRAM

GS8182S18D-267/250/200/167
Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so
results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep
both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands
and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from
loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random
address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs
offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore,
SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two
electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 SigmaSIO-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C
are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high).
SigmaSIO-II Double Data Rate SRAM Read First
Read A
Write B
Read C
Write D
NOP
Read E
Read F
NOP
K
K
Address
LD
R/W
BWx
D
C
C
Q
CQ
CQ
A
B
C
D
E
F
B
B+1
B
B+1
D
D+1
D
D+1
A
A+1
C
C+1
E
E+1
F
Rev: 1.08a 8/2005
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology