GS8182S18D Datasheet, PDF (31/31 Pages) GSI Technology – 18Mb Burst of 2 DDR SigmaSIO-II SRAM

GS8182S18D-267/250/200/167
SigmaSIO-II Revision History
File Name
8182Sxx_r1
8182Sxx_r1; 8182Sxx_r1_01
8182Sxx_r1_01; 8182Sxx_r1_02
8182Sxx_r1_02; 8182Sxx_r1_03
8182Sxx_r1_03; 8182Sxx_r1_04
8182Sxx_r1_04; 8182Sxx_r1_05
8182Sxx_r1_05; 8182Sxx_r1_06
8182Sxx_r1_06; 8182Sxx_r1_07
8182Sxx_r1_07; 8182Sxx_r1_08
Format/Content
Content
Content
Content
Content
Content
Content
Content
Content
Description of changes
Creation of datasheet
• Changed 330 MHz to 333MHz
• Removed any references to 133 MHz or 100 MHz
• Updated AC spec information
• Comprehensive rewrite, including (but not limited to)
tables, pinouts, and timing diagrams
• Removed x36 configuration
• Removed 333 and 300 MHz speed bins
• Updated format
• Updated timing diagrams
• Corrected erroneous VDD information in pin description
table
• Deleted erroneous sentent in FLXDrive section
• Added 165 BGA Pb-Free information
• Added Storage Under Bias information
• Incorporated IDD information into Operating Currents table
• Updated Test Conditions for Operating Currents table
• Added max numbers for tKHKH and tCHCH in AC Char.
table
• Added Clock to /Clock Delay timing to AC Char. table
• Updated timing diagrams
• Added 267 MHz speed bin
Rev: 1.08a 8/2005
31/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology