GA50SICP12-227_15 Datasheet, PDF (9/13 Pages) GeneSiC Semiconductor, Inc. – Silicon Carbide Junction Transistor/Schottky Diode Co-Pack

GA50SICP12-227
Ideally, I_G,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady on-
state. In practice, the rise time of the I_G,on pulse is affected by the parasitic inductances, L_par in the device package and drive circuit. A voltage
developed across the parasitic inductance in the source path, L_s, can de-bias the gate-source junction, when high drain currents begin to flow
through the device. The voltage applied to the gate pin should be maintained high enough, above the V_GS,sat (see Figure 7) level to counter
these effects.
A high negative peak current, -I_G,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. Turn off can be achieved with V_GS = 0 V, however a negative gate voltage V_GS may be used in order to
speed up the turn-off transition.
Gate Return Pin
The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the
GA50SICP12-227. Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in
all power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance,
however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency
gate driving.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4
The GA50SICP12-227 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a
gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while
in on-state. An evaluation gate drive board (GA15IDDJT22-FR4) utilizing this topology is commercially available low-side driving, its datasheet
provides additional details.
Gate
Signal
+12 V
Signal
R1 _U4
Signal RTN
GA15IDDJT22-FR4
Gate Driver Board
CG1
V_GL
V_GL
V_GH
R2
CG2
U2
U1
C6
R5
V_{EE C9} V_EE C10
V_EE ^C7
VCC High
C2 _X2
VCC High RTN
V_GL
C5
R6
V_GL
R3
U3
R4
D1
V_EE C8
RG1
RG2
D
I_G ^G
GR
S
+12 V
VCC Low
C1 _X1
VCC Low RTN
V_GH
C21
C4
V_EE
Figure 25: Topology of the GA15IDDJT22-FR4 Two Voltage Source gate driver.
The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance³ of RG = 0.7 Ω. It may be necessary for the user to reduce RG1 and/or RG2 under high drain current conditions for safe
operation of the GA50SICP12-227. The steady state current supplied to the gate pin of the GA50SICP12-227 with on-board RG = 0.7 Ω, is
shown in Figure 26. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 27.
For the GA50SICP12-227, R_G must be reduced or shorted for I_D ≥ ~60 A for safe operation with the GA15IDDJT22-FR4.
For operation at I_D ≥ ~60 A, R_G may be calculated from the following equation, which contains the DC current gain h_FE and the gate-source
saturation voltage V_GS,sat (Figure 7).
𝑅𝑅_{𝐺𝐺,𝑚𝑚𝑚𝑚}
=
�4.7𝑉𝑉
−
𝑉𝑉_{𝐺𝐺𝐺𝐺,í µí± í µí± í µí± í µí± í µí± í µí±}  � ∗
𝐼𝐼_{𝐷𝐷} ∗ 1.5
ℎ_{𝐹𝐹𝐹𝐹} (𝑇𝑇,
𝐼𝐼_{𝐷𝐷} )
−
0.1Ω
Dec 2015
Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/
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