MB86612 Datasheet, PDF(9/40 Page) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)

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MB86612 Datasheet, PDF (9/40 Pages) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)

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MB86612

s PIN DESCRIPTION

1. 1394 Interface

Pin name

TPA0

TPB0

TPA1

TPB1

TPBIAS0

TPBIAS1

RO0

RO1

I/O

Function

I/O Cable port 0 TPA positive signal I/O pin

I/O Cable port 0 TPA negative signal I/O pin

I/O Cable port 0 TPB positive signal I/O pin

I/O Cable port 0 TPB negative signal I/O pin

I/O Cable port 1 TPA positive signal I/O pin

I/O Cable port 1 TPA negative signal I/O pin

I/O Cable port 1 TPB positive signal I/O pin

I/O Cable port 1 TPB negative signal I/O pin

O Cable port 0 common voltage reference voltage output pin

O Cable port 1 common voltage reference voltage output pin

Connect to GND through 4.7 kâ¦ resistance

2. Isochronous-data Interface

Pin name

ICLK

IDIR

ILWRE

ID7 to ID0

I/O

Function

Isochronous data interface CLK signal input pin (DC to 16 MHz).

Note: When this clock is stopped, transfer is stopped. Also the âData FIFO init

(63h)â instruction (operand: 21) is invalid.

Isochronous transfer sending/receiving switching signal input pin.

0 input: Clear ISO FIFO, go to sending mode.

Sending starts after receiving 1 packet of data.

1 input: Clear ISO FIFO, go to receiving mode. If a â1â signal is entered during

packet sending, receiving mode begins after sending of the current packet.

The ILWRE signal is asserted after receiving 1 packet.

Note: This signal should normally be left at â1â, and switched to â0â only when

sending.

Isochronous FIFE access enable signal output pin.

Sending: Asserted when 1 or more empty source packets are present in ISO

FIFO.

O When negated, the data output up to the leading edge for the next ICLX.

Receiving: Asserted when receiving of 1 source packet of data is completed.

Negate conditions for this signal are determined by the ilwre-mode bit (bit 11) in

the mode-control register.

I/O Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0)

ID7 to ID0 enable signal input pin.

Sending: While this signal is active, data from the ID7 to ID0 pins is loaded into

ISO FIFO memory at the rising edge of the ICLK signal.

Receiving: While this signal is active, data from ISO FIFO memory is sent to the

ID7 to ID0 pins. Data is switched at the falling edge of the ICLK signal.

(Continued)

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