MB86612 Datasheet, PDF (36/40 Pages) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)

MB86612
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (MPEG, DVC) protocols.
Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh).
Address
HEX A5 A4 A3 A2 A1
Write operation
Read operation
10 0 1 0 0 0
Sending time stamp offset
setting register
Receiving time stamp
display register (high)
12 0 1 0 0 1
Sending time stamp offset
setting register
Receiving time stamp
display register (low)
14 0 1 0 1 0
Sending CIP header
setting register (highest)
Receiving CIP header
display register (highest)
16 0 1 0 1 1
Sending CIP header
setting register (high)
Receiving CIP header
display register (high)
18 0 1 1 0 0
Sending CIP header
setting register (low)
Receiving CIP header
display register (low)
1A 0 1 1 0 1
Sending CIP header
setting register (lowest)
Receiving CIP header
display register (lowest)
1C 0 1 1 1 0
OMPR (high)
←
1E 0 1 1 1 1
OMPR (low)
←
20 1 0 0 0 0
OPCR0 (high)
←
22 1 0 0 0 1
OPCR0 (low)
←
24 1 0 0 1 0
(reserved)
←
26 1 0 0 1 1
(reserved)
←
28 1 0 1 0 0
(reserved)
←
2A 1 0 1 0 1
(reserved)
←
2C 1 0 1 1 0
IMPR (high)
←
2E 1 0 1 1 1
IMPR (low)
←
30 1 1 0 0 0
IPCR0 (high)
←
32 1 1 0 0 1
IPCR0 (low)
←
34 1 1 0 1 0
(reserved)
←
36 1 1 0 1 1
(reserved)
←
38 1 1 1 0 0
(reserved)
←
3A 1 1 1 0 1
(reserved)
←
3C 1 1 1 1 0
AV mode setting register
AV status register
36