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MB86612 Datasheet, PDF (37/40 Pages) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)
MB86612
4. Bank 2 Registers
Bank 2 contains CSR’s.
Access to this bank is enabled by writing ‘0002h’ to the bank select register (3Eh).
Address
HEX A5 A4 A3 A2 A1
Write operation
Read operation
10 0 1 0 0 0
bus manager ID register (high)
←
12 0 1 0 0 1
bus manager ID register (low)
←
14 0 1 0 1 0 bandwidth available register (high)
←
16 0 1 0 1 1 bandwidth available register (low)
←
18 0 1 1 0 0 channels available high register (high)
←
1A 0 1 1 0 1 channels available high register (low)
←
1C 0 1 1 1 0 channels available low register (high)
←
1E 0 1 1 1 1 channels available low register (low)
←
20 1 0 0 0 0
(reserved)
←
22 1 0 0 0 1
(reserved)
←
24 1 0 0 1 0
(reserved)
←
26 1 0 0 1 1
(reserved)
←
28 1 0 1 0 0
(reserved)
←
2A 1 0 1 0 1
(reserved)
←
2C 1 0 1 1 0
(reserved)
←
2E 1 0 1 1 1
(reserved)
←
30 1 1 0 0 0
(reserved)
←
32 1 1 0 0 1
(reserved)
←
34 1 1 0 1 0
(reserved)
←
36 1 1 0 1 1
(reserved)
←
38 1 1 1 0 0
(reserved)
←
3A 1 1 1 0 1
(reserved)
←
3C 1 1 1 1 0
(reserved)
←
37