MB86612 Datasheet, PDF (11/40 Pages) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)

MB86612
4. Other
Pin name
X0
X1
VCOIN
CHPO
ROP
RESET
MODE0
MODE1
PMODE
PWR1 to PWR3
BUSRST
LINKON
AVDD
AVSS
VDD
VSS
TESTP
I/O
Function
I/O
External crystal connection pins for oscillator circuits.
I
I
VCO input pin for internal PLL.
O Charge pump output pin for internal PLL.
O
Connect to GND through 4.7 kΩ resistance.
I
Reset signal input pin.
This signal should be set to ‘0’ when the system power supply is off.
I
Input ‘0’ for 80-series mode.
Input ‘1’ for 68-series mode.
I
Input ‘0’ for non-multiplexed mode.
Input ‘1’ for multiplexed mode.
I
For cable power supply, set to ‘0’ for power startup.
Set to ‘1’ when cable power supply is off or until system power is on.
When operating from cable power supply, these pins determine the value of the
I
‘POWER_CLASS’ area of Self-ID packets.
When operating from system power supply, these pins correspond to the power
bit in the Self-ID-PKT-param setting register.
When the MB86612 is started from the power supply this bit determines whether
a bus reset is applied automatically.
I
Input ‘0’ for no bus reset.
Input ‘1’ for bus reset.
When this bit is set to ‘1’, a bus reset is executed 200 µs after the int-reset bit (bit
9) in the flag & status register (address 02h) is set to ‘1’.
Link-on packet receiving detection pin. Outputs an ‘H’ signal for 1 to 2 tclk (1 to 2
O cycles of the crystal oscillator input signal) when a link-0n packet is received.
When this signal is not used, leave it open.
— Analog power supply
— Analog ground
— Digital power supply
— Digital ground
— Test pin. Do not connect.
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