MB86612 Datasheet, PDF (12/40 Pages) Fujitsu Component Limited. – IEEE 1394 Bus Controller (for MPEG, DVC)

MB86612
s BLOCK DIAGRAM
IDIR
ICLK
ILWRE
ID7 to ID0
IV
TS
IERR
CTR
OCLK
CS
A5 to A1
D15 to D6, D0
AD5 to AD1
RD (R/W)
WR (DS)
ALE
INT
ISO
sending
packet
control
ISO
receiving
packet
control
LINK
layer
control
circuit
PHY
layer
control
circuit
ASYNC
send-only
FIFO
(128 byte)
ASYNC
sending
packet
processing
ASYNC
receive-only
FIFO
(128 byte)
ASYNC
receiving
packet
processing
Cycle mask
TPA0
TPA0
TPB0
TPB0
TPBIAS0
TPA1
TPA1
TPB1
TPB1
TPBIAS1
Transaction circuit block
Register block
CSR
PLL circuit
12