MB81EDS516445 Datasheet, PDF (4/52 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516445
6. Address Inputs (A0 to A12)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. Total 21
address input signals are required to decode such a matrix. Row Address (RA) is input from A0 to A12 and
Column Address (CA) is input from A0 to A7. Row addresses are latched with ACTIVE (ACT) command, and
Column addresses and Auto Precharge (AP) bit are latched with Read (READ or READA) or Write command
(WRIT or WRITA).
• Command and address inputs setup and hold time
CK
Command
(CS, RAS, CAS, WE)
Address
tIS tIH
tIPW
7. Input Data Mask (DM0 to DM7)
DM is an input mask signal for write data. Input data is masked when DM is sampled High on the both edges
of DQS along with input data. DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0],
DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56] respectively. Refer to the
“DQ/DQS/DM Correspondence Table”.
8. Data Bus Input / Output (DQ0 to DQ63)
DQ is data bus input / output signal.
9. Data Strobe (DQS0 to DQS7)
DQS is edge aligned with output read data and center aligned with input write data. DQS0, DQS1, DQS2, DQS3,
DQS4, DQS5, DQS6 and DQS7 correspond to DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40],
DQ[55:48] and DQ[63:56] respectively. Refer to the “DQ/DQS/DM Correspondence Table”.
• DQ/DQS/DM Correspondence Table
DQ
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
DQS
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DM
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
4
DS05-11464-1E