MB81EDS516445 Datasheet, PDF (18/52 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516445
■ BANK OPERATION COMMAND TABLE
Minimum clock latency or delay time for single bank operation
2nd Command (same bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
ACT
⎯
READ
⎯
READA
WRIT
WRITA
READ -
BST
WRIT -
BST
PRE
*1, *2
BL/2
+ tRP
⎯
*1, *2
BL/2
+1
+ tDAL
⎯
⎯
*1, *2
tRP
PALL
*2
tRP
REF
tREFC
⎯
⎯
BL/2
+ tRP
⎯
BL/2
+1
+ tDAL
⎯
⎯
tRP
tRP
tREFC
tRCD
1
*4
tRCD
1
⎯
*6
2
+ tWTR
⎯
⎯
*6
2
+ tWTR
⎯
1
1
+ tWTR
⎯
1
1
+ tWTR
⎯
⎯
⎯
⎯
⎯
tRCD
*6
BL/2
+CL
⎯
1
⎯
CL
1
⎯
⎯
⎯
*5
tRCD
*6
BL/2
+CL
⎯
1
⎯
CL
1
⎯
⎯
⎯
⎯
1
BL/2
+ tRP
1
BL/2
+1
+ tDAL
1
tRP
tRP
tREFC
SELFX
tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
“ - ” : illegal
*1: Assume all banks are in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRAS (Min.) is satisfied.
*4: ACT to READA interval must be longer than tRAS - BL/2.
*5: ACT to WRITA interval must be longer than tRAS - (1 + BL/2 + tWR).
*6: Assume appropriate DM masking.
tMRD
tRAS
*3
1
BL/2
+ tRP
*3
BL/2
+1
+ tWR
BL/2
+1
+ tDAL
*3
1
*3
1
+ tWR
1
1
tREFC
tREFC
tMRD
tRAS
*3
1
BL/2
+ tRP
*3
BL/2
+1
+ tWR
BL/2
+1
+ tDAL
*3
1
*3
1
+ tWR
1
1
tREFC
tREFC
tMRD
⎯
⎯
*1
BL/2
+ tRP
⎯
*1
BL/2
+1
+ tDAL
⎯
⎯
*1
tRP
tRP
tREFC
tREFC
tMRD
⎯
⎯
*1, *2
BL/2
+ tRP
⎯
*1, *2
BL/2
+1
+ tDAL
⎯
⎯
*1, *2
tRP
*2
tRP
tREFC
tREFC
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DS05-11464-1E