MB81EDS516445 Datasheet, PDF (19/52 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516445
Minimum clock latency or delay time for multi bank operation
2nd Command (other bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
tMRD
tMRD
tMRD
tMRD
ACT
⎯
READ
READA
WRIT
WRITA
READ -
BST
WRIT -
BST
PRE
PALL
REF
⎯
*1, *2
BL/2
+ tRP
⎯
*1
BL/2
+1
+ tDAL
⎯
⎯
*1, *2
tRP
*1
tRP
tREFC
tRRD
*1, *3
1
*1, *3
1
*1, *3
1
*1, *3
1
*1, *3
1
*1, *3
1
tRP
tREFC
1
1
1
1
BL/2
*5
2
+ tWTR
*5
BL/2
+1
+ tWTR
1
1
+ tWTR
1
BL/2
*5
2
+ tWTR
*5
BL/2
+1
+ tWTR
1
1
+ tWTR
1
1
*5
BL/2
+CL
*5
BL/2
+CL
1
BL/2
CL
1
1
⎯
⎯
⎯
⎯
⎯
⎯
1
*5
BL/2
+CL
*5
BL/2
+CL
1
BL/2
CL
1
1
⎯
⎯
1
1
BL/2
+ tRP
1
BL/2
+1
+ tDAL
1
1
tRP
tREFC
1
1
1
1
1
1
1
1
1
tREFC
tRAS
*4
1
*4
BL/2
+ tRP
*4
BL/2
+1
+ tWR
*4
BL/2
+1
+ tDAL
*4
1
*4
1
+ tWR
1
1
⎯
⎯
*1
BL/2
+ tRP
⎯
*1
BL/2
+1
+ tDAL
⎯
⎯
*1
tRP
tRP
⎯
⎯
*1
BL/2
+ tRP
⎯
*1
BL/2
+1
+ tDAL
⎯
⎯
*1, *2
tRP
tRP
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
“ - ” : illegal
*1: Assume other bank is in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRRD is satisfied.
*4: Assume tRAS is satisfied.
*5: Assume appropriate DM masking.
DS05-11464-1E
19