MB81EDS516445 Datasheet, PDF (24/52 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516445
Write Preamble and Postamble
CK
CK
Command _WRITE
DQS
DQ
tWPRES
tWPRE
Q0 Q1 Q2 Q3
NOP
Q4 Q5
tWPST
Q6 Q7
7. WRITE with Auto Precharge (WRITA)
WRITA commands can be issued by WRIT command with AP (A10) = H. Auto precharge is a feature which
precharge the activated bank after the completion of burst write operation. The tRAS is defined from between
ACTIVE (ACT) command to the internal precharge which starts after 1+ BL/2 + tWR from WRITA command. WRIT
with Auto precharge operation should not be interrupted by subsequent READ, READA, WRIT, WRITA
commands. Next ACTIVE (ACT) command can be issued after 1+ BL/2 + tDAL after WRITA command.
8. BURST TERMINATE (BST)
BST terminates the burst read or write operation. When a burst read is terminated by BST command, the data
output will be in High-Z after CAS latency from the BST command. When a burst write is terminated by BST
command, the data input after 1 clock from BST command will be masked.
Terminate read by BST @CL=3
CK
Command
NOP
DQ (output)
READ
CL = 3
BST
CL = 3
NOP
Q0
Q1
Terminate write by BST
CK
Command
NOP
DQ (input)
WRIT
1 clock
BST
D0
D1
NOP
Masked
by BST
D2
D3
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DS05-11464-1E