MB82DBS02163D-70L Datasheet, PDF (21/57 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163D-70L
(2) Asynchronous Write Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Symbol
Value
Min
Max
Unit Notes
Write Cycle Time
Address Setup Time
ADV Low Pulse Width
ADV High Pulse Width
Address Setup Time to ADV High
Address Hold Time from ADV High
CE1 Write Pulse Width
WE Write Pulse Width
LB, UB Write Pulse Width
LB, UB Byte Mask Setup Time
LB, UB Byte Mask Hold Time
Write Recovery Time
CE1 High Pulse Width
WE High Pulse Width
LB, UB High Pulse Width
Data Setup Time
Data Hold Time
OE High to CE1 Low Setup Time for Write
OE High to Address Setup Time for Write
LB and UB Write Pulse Overlap
tWC
tAS
tVPL
tVPH
tASV
tAHV
tCW
tWP
tBW
tBS
tBH
tWR
tCP
tWHP
tBHP
tDS
tDH
tOHCL
tOES
tBWO
70
1000
ns *1, *2
0
⎯
ns *3
10
⎯
ns *4
10
⎯
ns *4
10
⎯
ns *5
5
⎯
ns *5
45
⎯
ns *3
45
⎯
ns *3
45
⎯
ns *3
−5
⎯
ns *6
−5
⎯
ns *7
0
⎯
ns *8
10
⎯
ns
10
1000
ns
10
1000
ns
15
⎯
ns
0
⎯
ns
−5
⎯
ns *9
0
⎯
ns *10
40
⎯
ns
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery
time (tWR).
*3 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last.
*4 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
*5 : The sum of actual tASV and tAHV must be equal or greater than 10 ns.
*6 : Applicable for byte mask only. Byte mask setup time is defined from the High to Low transition of CE1 or WE
whichever occurs last.
*7 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*8 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first.
*9 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within
5 ns after CE1 is brought to Low.
*10 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at
the same time or before the new address is valid.
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