MB82DBS02163D-70L Datasheet, PDF (12/57 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163D-70L
• WAIT Output Function
The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst
mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L
whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output
becomes High one clock cycle prior to a valid data output. During OE read suspend, WAIT output does not
indicate the data bus status but carries the same level from previous clock cycle (kept High) except for read
suspend on the final data output. If final read data output is suspended, WAIT output becomes high impedance
after specified time duration from OE = H.
During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or
CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual
write data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and
Burst Length. During WE Write suspend, WAIT output does not indicate the data bus status but carries the same
level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data
input is suspended, WAIT output becomes high impedance after specified time duration from WE = H.
This device does not incur additional delay against crossing device-row boundary or internal refresh operation.
Therefore, the burst operation is always started after the fixed latency with respect to Read Latency. And there
is no waiting cycle asserted in the middle of burst operation except for burst suspend by OE brought to High or
WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keep High level until
the end of burst or until the burst operation is terminated.
When the device is operating in the asynchronous mode, WAIT output is always in High Impedance.
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR set sequence after power-up. Once
specific RL is set through CR set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1.
The burst operation is always started after the fixed latency with respect to Read Latency set in CR.
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