MB82DP02183C-65L Datasheet, PDF (10/32 Pages) Fujitsu Component Limited. – 32M Bit (2 M word × 16 bit) Mobile Phone Application Specific Memory

MB82DP02183C-65L
(2) WRITE OPERATION
Parameter
Write Cycle Time
Address Setup Time
CE1 Write Pulse Width
WE Write Pulse Width
LB, UB Write Pulse Width
LB, UB Byte Mask Setup Time
LB, UB Byte Mask Hold Time
Write Recovery Time
CE1 High Pulse Width
WE High Pulse Width
LB, UB High Pulse Width
Data Setup Time
Data Hold Time
OE High to CE1 Low Setup Time for Write
OE High to Address Setup Time for Write
LB and UB Write Pulse Overlap
Symbol
tWC
tAS
tCW
tWP
tBW
tBS
tBH
tWR
tCP
tWHP
tBHP
tDS
tDH
tOHCL
tOES
tBWO
Value
Min
Max
65
1000
0
⎯
40
⎯
40
⎯
40
⎯
−5
⎯
−5
⎯
0
⎯
12
⎯
12
1000
12
1000
12
⎯
0
⎯
−5
⎯
0
⎯
30
⎯
Unit
Notes
ns *1, *2
ns *3
ns *3
ns *3
ns *3
ns *4
ns *5
ns *6
ns
ns
ns
ns
ns
ns *7
ns *8
ns
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
*3 : Write pulse is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last.
*4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
whichever occurs last.
*5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*6 : Write recovery is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first.
*7 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1 is brought to Low.
*8 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid.
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