DS_FT313H Datasheet, PDF (24/64 Pages) Future Technology Devices International Ltd. – The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s.

Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
Bit
Name
0
RS
Type
R/W
Table 5-5 USB command register
Default value
1’b0
Description
Run/Stop
When this bit is set to 1b, the host controller
proceeds with the execution of schedule.
0: Stop
1: Run
5.2.5 USBSTS register (address = 14h)
This register indicates pending interrupts and various states of the Host Controller. The status resulting
from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this
register by writing a 1 to it.
Bit
Name
Type Default value Description
[31:16] Reserved
RO
16’h0
15
ASCH_STS
RO
1’b0
14
PSCH_STS
RO
1’b0
13
Reclamation RO
1’b0
12
HCHalted
RO
1’b1
[11:6]
5
Reserved
INT_OAA
RO
6’b0
R/WC 1’b0
4
H_SYSERR
R/WC 1’b0
3
FRL_ROL
R/WC 1’b0
2
PO_CHG_DET R/WC 1’b0
-
Asynchronous Schedule Status
This bit reports the actual status of the
asynchronous schedule.
Periodic Schedule Status
This bit reports the actual status of the periodic
schedule.
Reclamation
This is a read-only status bit, and used to detect
an empty of the asynchronous schedule.
Host Controller Halted
This bit is a zero whenever the Run/Stop bit is
set to ‘1.’ The host controller sets this bit to ‘1’
after it has stopped the executing as a result of
the Run/Stop bit being set to 0b.
-
Interrupt on Asynchronous Advance
This status bit indicates the assertion of interrupt
on Async Advance Doorbell.
Host System Error
The Host Controller sets this bit to ‘1’ when a
serious error occurred during a host system
access involving the host controller module.
Frame List Rollover
The host controller sets this bit to ’1’ when the
Frame List Index rolls over from its maximum
value to zero.
Port Change Detect
The host controller sets this bit to ’1’ when any
port has a change bit transition from ‘0’ to ‘1.’
In addition, this bit is loaded with the OR of all of
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