MC9S12P64CFT Datasheet, PDF (86/566 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12PPIMV1)
2.3.38 Port M Wired-Or Mode Register (WOMM)
Address 0x0256
7
R
0
W
Reset
0
1. Read: Anytime
Write: Anytime
6
5
4
3
2
0
WOMM5 WOMM4 WOMM3 WOMM2
0
0
0
0
0
Figure 2-36. Port M Wired-Or Mode Register (WOMM)
Access: User read/write⁽¹⁾
1
0
WOMM1
WOMM0
0
0
Table 2-34. WOMM Register Field Descriptions
Field
Description
5-0
WOMM
Port M wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active
low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no
influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
2.3.39 PIM Reserved Register
Address 0x0257
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1. Read: Always reads 0x00
Write: Unimplemented
Figure 2-37. PIM Reserved Register
Access: User read⁽¹⁾
1
0
0
0
0
0
S12P-Family Reference Manual, Rev. 1.13
86
Freescale Semiconductor