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MC9S12P64CFT Datasheet, PDF (105/566 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Port Integration Module (S12PPIMV1)
2.4.4 Pin interrupts
Ports P and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually conï¬gured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins conï¬gured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt ï¬ag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital ï¬lter on each pin prevents pulses (Figure 2-66) shorter than a speciï¬ed time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-65 and
Table 2-60).
Glitch, ï¬ltered out, no interrupt ï¬ag set
Valid pulse, interrupt ï¬ag set
uncertain
tpign
tpval
Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0)
Table 2-60. Pulse Detection Criteria
Mode
Pulse
STOP
STOP(1)
Unit
Ignored
tpulse ⤠3 bus clocks
tpulse ⤠tpign
Uncertain
3 < tpulse < 4 bus clocks
tpign < tpulse < tpval
Valid
tpulse ⥠4 bus clocks
tpulse ⥠tpval
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
105
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