MCF5206FT33A Datasheet, PDF (84/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
Instruction Cache
4.3.1 Interaction With Other Modules
Since the instruction cache and high-speed SRAM module are connected to the ColdFire
core's local data bus, certain user-defined configurations can result in simultaneous
instruction fetch processing.
If the referenced address is mapped into the SRAM module, that module will service the
request in a single cycle. In this case, data accessed from the instruction cache is simply
discarded, and no external memory references are generated. If the address is not
mapped into the SRAM space, the instruction cache handles the request in the normal
fashion.
4.3.2 Memory Reference Attributes
For every memory reference the ColdFire core or the Debug module generates, a set of
Òeffective attributesÓ is determined based on the address and the Access Control
Registers (ACR0, ACR1). This set of attributes includes the cacheable/noncacheable
definition, the precise/imprecise handling of operand write, and the write-protect
capability.
In particular, each address is compared to the values programmed in the Access Control
Registers (ACR). If the address matches one of the ACR values, the access attributes
from that ACR are applied to the reference. If the address does not match either ACR,
then the default value defined in the Cache Control Register (CACR) is used. The specific
algorithm is as follows:
if (address = ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address = ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
4.3.3 Cache Coherency and Invalidation
The instruction cache does not monitor ColdFire core data references for accesses to
cached instructions, therefore software must maintain cache coherency by invalidating
the appropriate cache entries after modifying code segments.
The cache invalidation can be performed in two ways. The assertion of bit 24 in the CACR,
via a CPU space write, forces the entire instruction cache to be marked as invalid. The
invalidation operation requires 32 cycles because the cache sequences through the entire
tag array, clearing a single location each cycle. Any subsequent instruction fetch
accesses are postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this
instruction is executed, the cache entry defined by bits[8:4] of the source address register
is invalidated, provided bit 28 of the CACR is cleared.
MOTOROLA
MCF5206 USERÕS MANUAL Rev 1.0
4-3
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