MCF5206FT33A Datasheet, PDF (167/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
Bus Operation
ALTERNATE MASTER
1. DRIVE ADDRESS ON A[27:0]
2. DRIVE R/W TO READ (R/W = 1)
3. DRIVE SIZ[1:0] TO INDICATE
WORD, LONGWORD OR LINE
4. ASSERT TS FOR ONE CLK CYCLE
MCF5206
1. REGISTER ALTERNATE
MASTER A[27:0], R/W , SIZ[1:0]
SYSTEM
1. NEGATE TS
1. REGISTER DATA
2. RECOGNIZE THE 1ST
TRANSFER IS DONE
3. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON
SIZ[1:0], A[3:0] AND PORT SIZE
1. REGISTER DATA
2. RECOGNIZE THE 2ND
TRANSFER IS DONE
3. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON
SIZ[1:0], A[3:0] AND PORT
SIZE
1. REGISTER DATA
2. RECOGNIZE THE 3RD
TRANSFER IS DONE
3. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON
SIZ[1:0], A[3:0] AND PORT SIZE
1. REGISTER DATA
2. RECOGNIZE THE 4TH
TRANSFER IS DONE
1. DRIVE TA TO NEGATED STATE*
2. LOAD WAIT STATE COUNTER
WITH APPROPRIATE COUNT
VALUE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. NEGATE TA FOR ONE CLK
CYCLE
1. THREE-STATE TA .
1. DECODE ADDRESS AND
SELECT THE APPROPRIATE
SLAVE DEVICE
1. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DECODEADDRESSANDSELECT
THE APPROPRIATE SLAVE
DEVICE
2. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DECODE ADDRESS AND
SELECT THE APPROPRIATE
SLAVE DEVICE
2. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DECODEADDRESSANDSELECT
THE APPROPRIATE SLAVE
DEVICE
2. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
Figure 6-45. Alternate Master Bursting Read Transfer Using MCF5206-Generated
Transfer-Acknowledge Flowchart
MOTOROLA
MCF5206 USERÕS MANUAL Rev 1.0
6-73
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