MCF5206FT33A Datasheet, PDF (41/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
Introduction
1.3.3 Internal SRAM
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The 512-byte on-chip SRAM provides one clock-cycle access for the ColdFire core. This
SRAM can store processor stack and critical code or data segments to maximize
performance.
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1.3.4 DRAM Controller
The MCF5206 DRAM controller provides a glueless interface for as many as two banks of
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DRAM, each of which can be from 128 Kbytes to 256 Mbytes in size. The controller supports
an 8-, 16-, or 32-bit data bus. A unique addressing scheme allows for increases in system
memory size without rerouting address lines and rewiring boards. The controller operates in
fast page mode, burst-page mode, or normal mode, and supports extended-data-out (EDO)
DRAMs.
DRAM operations are available to other external bus masters. The DRAM controller can
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generate CAS and RAS for an external master and can continue to manage refresh
requests.
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1.3.5 DUART Module
A full duplex DUART module contains independent receivers and transmitters that can be
clocked by the DUART internal timer. This timer is clocked by the system clock or an
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external clock supplied by the TIN pin. Data formats can be 5, 6, 7, or 8 bits with even, odd,
or no parity, and as many as 2 stop bits in 1/16 increments. Four-byte receive buffers and
two-byte transmit buffers minimize CPU service calls. The DUART module also provides
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several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function via a programmable prescaler. You can
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select full duplex, autoecho loopback, local loopback, and remote loopback modes. The
programmable DUART can interrupt the CPU on various normal or error-condition events.
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1.3.6 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-
running 16-bit timer for use in any of three modes. One mode captures the timer value with
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an external event. Another mode triggers an external signal or interrupts the CPU when the
timer reaches a set value, while a third mode counts external events. The timer unit has an
8-bit prescaler that allows for programming the clock input frequency, which is derived from
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the system clock. The programmable timer-output pin generates either an active-low pulse
or toggles the output.
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1.3.7 Motorola Bus (M-Bus) Module
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The M-Bus interface is a two-wire, bidirectional serial bus that exchanges data between
devices and is compatible with the I²C Bus standard. The M-Bus minimizes the
interconnection between devices in the end system and is best suited for applications that
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need occasional bursts of rapid communication over short distances among several
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MCF5206 USERÕS MANUAL Rev 1.0
MOTOROLA
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