MCF5206FT33A Datasheet, PDF (281/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
DRAM Controller
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When using the MCF5206 to multiplex the address for external master DRAM transfers
(DAEM bit in the DCTR is set), the external master must stop driving the address bus
during the clock cycle after TS is asserted. This allows the MCF5206 to drive the row
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address and the column address on A[27:9] at the appropriate times. If the external
master cannot three-state the address bus, the driving of the address by the MCF5206
should be disabled and the address multiplexing for external master transfers must be
handled in the external system.
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If address multiplexing for external master transfers is to be handled in the external
system, the DRAMC must be configured to three-state the address bus during these
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transfers by clearing the DAEM bit in the DCTR. This does not affect the operation of TA,
RAS, CAS, or DRAMW during external master DRAM transfers.
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NOTE
The MCF5206 does not drive the address for external master
chip select or default memory transfers.
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10.3.8.1 EXTERNAL MASTER NONBURST TRANSFER IN NORMAL MODE. An
external master nonburst transfer to DRAM is generated when the operand size is the
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same or smaller than the DRAM port size (e.g., longword transfer to a 32-bit port or byte
transfer to a 16-bit port). The external master must assert TS at the start of all non-burst
transfers.
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The timing of nonburst reads and nonburst writes is identical in normal page mode, with
the exception of when the DRAM drives data on reads and when the external master
drives data on writes.
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The fastest possible nonburst transfer in normal mode requires 5 clocks. You can program
the DCTR to generate slower normal mode transfers.
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MOTOROLA
MCF5206 USERÕS MANUAL Rev 1.0
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10-41
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