MCF5206FT33A Datasheet, PDF (56/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
Signal Description
bank, and CAS[0] for an 8-bit wide DRAM bank. Table 2-9 shows which CAS signals are
asserted based on the operand size, the DRAM port size, and the address bits A[1:0]. You
can customize CAS timing to match the specifications of the DRAM by programming the
DRAM Controller Timing Register (see Section 10.4.2.2. DRAM Controller Timing
Register (DCTR).).
.
Table 2-9. CAS Assertion
OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] A[1]
8-bit
BYTE
16-bit
32-bit
WORD
8-bit
16-bit
32-bit
LONG WORD
LINE
8-bit
16-bit
32-bit
8-bit
16-bit
32-bit
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
CAS[0] CAS[1] CAS[2] CAS[3]
A[0]
D[31:24] D[23:16] D[15:8] D[7:0]
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
MOTOROLA
MCF5206 USERÕS MANUAL Rev 1.0
2-13
For More Information On This Product,
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