MCF5206FT33A Datasheet, PDF (63/449 Pages) Freescale Semiconductor, Inc – ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

Freescale Semiconductor, Inc.
Signal Description
Table 2-11. MCF5206 Signal Summary (Continued)
SIGNAL NAME
Bus Driven
Clock Input
Reset
Row Address Strobe
MNEMONIC
BD
CLK
RSTI
RAS[1:0]
Column Address Strobe
CAS[3:0]
DRAM Write
Receive Data
Transmit Data
Request-To-Send
Request-To-Send
Clear-To-Send
Timer Input
Timer Output
Serial Clock Line
Serial Data Line
General Purpose I/O/ Processor
Status
General Purpose I/O/
Debug Data
Test Clock
Test Data Output/Development
Serial Output
Test Mode Select/ Break Point
Test Data Input / Development
Serial Input
Test Reset/Development Serial
Clock
Motorola Test Mode
High Impedance
DRAMW
RxD[1], RxD[2]
TxD[1], TxD[2]
RTS[1]
RTS[2]/
RSTO
CTS[1], CTS[2]
TIN[1], TIN[2]
TOUT[1], TIN[2]
SCL
SDA
PP[7:4]/
PST[3:0]
PP[3:0]/
DDATA[3:0]
TCK
TDO/
DSO
TMS/
BKPT
TDI/
DSI
TRST/
DSCLK
MTMOD
HIZ
INPUT/OUTPUT
Out
In
In
Out
Out
Out
In
Out
Out
Out/
Out
In
In
Out
In,Out
In,Out
In.Out/
Out
In,Out/
Out
In
Out/
Out
In/
In
In/
In
In/
In
In
In
ACTIVE STATE
Low
-
Low
Low
Low
Low
-
-
Low
Low/
Low
Low
-
-
Low
Low
-/
-
-/
-
-
-/
-
-/
Low
-/
-
Low/
-
-
Low
RESET STATE
Negated
-
-
Master Reset - Negated
Normal Reset - Unaffected
Master Reset - Negated
Normal Reset - Unaffected
Negated
-
Asserted
Negated
Asserted
-
-
Asserted
Negated
Negated
Three-stated
Three-stated
-
Three-Stated/
Negated
-/
-
-/
-
-/
-
-
-
2-20
MCF5206 USERÕS MANUAL Rev 1.0
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com