K51P144M100SF2 Datasheet, PDF (72/74 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Revision History
1
2
A
PTD7
PTD6
3
PTD5
4
PTD4
5
6
7
8
PTD0
PTC16
PTC12
PTC8
9
10
11
PTC4
VCAP1
PTC3
12
PTC2
A
B PTD12
PTD11
PTD10
PTD3
PTC19
PTC15
PTC11
PTC7
VLL1
VCAP2
PTC1
PTC0
B
C PTD15
PTD14
PTD13
PTD2
PTC18
PTC14
PTC10
PTC6
VLL2
VLL3
PTB23
PTB22 C
D
PTE2
PTE1
PTE0
PTD1
PTC17
PTC13
PTC9
PTC5
PTB21
PTB20
PTB19
PTB18 D
E
PTE6
PTE5
PTE4
PTE3
VDD
VDD
VDD
VDD
PTB17
PTB16
PTB11
PTB10 E
F PTE10
PTE9
PTE8
PTE7
VDD
VSS
VSS
VDD
PTB9
PTB8
PTB7
PTB6
F
G VOUT33
VREGIN
PTE12
PTE11
VREFH
VREFL
VSS
VSS
PTB5
PTB4
PTB3
PTB2
G
H USB0_DP USB0_DM
VSS
PTE28
VDDA
VSSA
VSS
VSS
PTB1
PTB0
J
ADC0_DP1/
OP0_DP0
ADC1_DP1/
K OP1_DP0/
OP1_DM1
ADC0_DM1/
OP0_DM0
ADC1_DM1/
OP1_DM0
ADC0_SE16/
OP0_OUT/
CMP1_IN2/
ADC0_SE21/
OP0_DP1/
OP1_DP1
DAC1_OUT/
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
ADC1_SE16/
OP1_OUT/
CMP2_IN2/
ADC0_SE22/
OP0_DP2/
OP1_DP2
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
OP0_DP4/
OP1_DP4
PTA0
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
PGA0_DP/
L ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
TRI0_OUT/
OP1_DM2
TRI0_DM
TRI1_DM
PTA1
PTA2
VBAT
PTA6
PTA3
PTA4
PTA7
PTA13
PTA27
PTA8
PTA12
PTA16
PTA9
PTA11
PTA14
PGA1_DP/
M ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
TRI0_DP
TRI1_DP
EXTAL32
XTAL32
PTA5
PTA10
VSS
1
2
3
4
5
6
7
8
9
10
Figure 31. K51 144 MAPBGA Pinout Diagram
PTA29
PTA28 H
PTA26
PTA25
J
PTA17
PTA24
K
PTA15
RESET_b L
PTA19
11
PTA18
M
12
9 Revision History
The following table provides a revision history for this document.
Table 51. Revision History
Rev. No.
2
Date
3/2011
Substantial Changes
Initial public revision
Table continues on the next page...
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
72
Preliminary
Freescale Semiconductor, Inc.