K51P144M100SF2 Datasheet, PDF (31/74 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

6.4.1.2
Peripheral operating requirements and behaviors
Flash timing specifications — commands
Table 19. Flash command timing specifications
Symbol Description
Read 1s Block execution time
t_rd1blk256k
• 256 KB data flash
Min.
—
Typ.
—
Max.
1.4
Unit
Notes
ms
t_rd1sec2k Read 1s Section execution time (flash sector)
—
—
40
μs
1
t_pgmchk Program Check execution time
—
—
35
μs
1
t_rdrsrc Read Resource execution time
—
—
35
μs
1
t_pgm4 Program Longword execution time
—
50
TBD
μs
Erase Flash Block execution time
2
t_ersblk256k
• 256 KB data flash
—
160
800
ms
t_ersscr Erase Flash Sector execution time
Program Section execution time
t_pgmsec512
t_pgmsec1k
t_pgmsec2k
• 512 B flash
• 1 KB flash
• 2 KB flash
t_rd1all Read 1s All Blocks execution time
t_rdonce Read Once execution time
t_pgmonce Program Once execution time
t_ersall Erase All Blocks execution time
t_vfykey Verify Backdoor Access Key execution time
—
20
100
ms
2
—
TBD
TBD
ms
—
TBD
TBD
ms
—
TBD
TBD
ms
—
—
2.8
ms
—
—
35
μs
1
—
50
TBD
μs
—
320
1600
ms
2
—
—
35
μs
1
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
I_{DD_PGM}
Description
Worst case programming current in program flash
Typ.
Unit
10
mA
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Symbol Description
t_nvmretp10k Data retention after up to 10 K cycles
t_nvmretp1k Data retention after up to 1 K cycles
Min.
Program Flash
5
10
Typ.¹
TBD
TBD
Max.
—
—
Table continues on the next page...
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
Unit
years
years
Notes
2
2
31