K51P144M100SF2 Datasheet, PDF (41/74 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA operating conditions (continued)
Symbol
R_PGAD
Description
Differntial input
impedance
R_AS Analog source
resistance
T_S
ADC sampling
time
Conditions
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Min.
—
—
—
—
1.25
Typ.¹
128
64
32
100
—
Max.
—
—
—
—
—
Unit
kΩ
Ω
µs
Notes
IN+ to IN-⁴
5
6
1. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 27. 16-bit ADC with PGA characteristics
Symbol
I_{DDA_PGA}
I_{DC_PGA}
Description
Supply current
Input DC current
Conditions
Min.
Typ.¹
Max.
Unit
—
590
TBD
μA
A
Notes
2
I_ILKG
G
Input Leakage
current
Gain⁴
BW
PSRR
Input signal
bandwidth
Power supply
rejection ration
PGA disabled
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
• 16-bit modes
• < 16-bit modes
Gain=1
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
TBD
TBD
0.98
1.99
3.97
7.95
15.8
31.4
61.2
—
—
TBD
Table continues on the next page...
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
4
40
—
μA
3
R_AS < 100Ω
kHz
kHz
dB
V_DDA= 3V
±100mV,
f_VDDA= 50Hz,
60Hz
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
41