M68HC11K_13 Datasheet, PDF (65/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Control Registers
NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Register Name
Port A Data Register ^Read:
(PORTA) Write:
See page 138. _Reset:
Port A Data Direction ^Read:
Register (DDRA) Write:
See page 138. _Reset:
Port B Data Direction ^Read:
Register (DDRB) Write:
See page 139. _Reset:
Port F Data Direction ^Read:
Register (DDRF) Write:
See page 144. _Reset:
Port B Data Register ^Read:
(PORTB) Write:
See page 139. _Reset:
Port F Data Register ^Read:
(PORTF) Write:
See page 144. _Reset:
Port C Data Register ^Read:
(PORTC) Write:
See page 140. _Reset:
Port C Data Direction ^Read:
Register (DDRC) Write:
See page 141. _Reset:
Port D Data Register ^Read:
(PORTD) Write:
See page 142. _Reset:
Port D Data Direction ^Read:
Register (DDRD) Write:
See page 142. _Reset:
Bit 7
PA7
DDA7
0
DDB7
0
DDF7
0
PB7
PF7
PC7
DDC7
0
0
0
0
0
6
5
PA6
PA5
DDA6
0
DDB6
0
DDF6
0
PB6
DDA5
0
DDB5
0
DDF5
0
PB5
PF6
PF5
PC6
PC5
DDC6 DDC5
0
0
0
PD5
0
U
0
DDD5
0
0
= Unimplemented
4
3
2
1
Bit 0
PA4
PA3
PA2
PA1
PA0
Undefined after reset
DDA4 DDA3 DDA2 DDA1 DDA0
0
0
0
0
0
DDB4 DDB3 DDB2 DDB1 DDB0
0
0
0
0
0
DDF4 DDF3 DDF2 DDF1 DDF0
0
0
0
0
0
PB4
PB3
PB2
PB1
PB0
Undefined after reset
PF4
PF3
PF2
PF1
PF0
Undefined after reset
PC4
PC3
PC2
PC1
PC0
Undefined after reset
DDC4 DDC3 DDC2 DDC1 DDC0
0
0
0
0
0
PD4
PD3
PD2
PD1
PD0
U
U
U
U
U
DDD4 DDD3 DDD2 DDD1 DDD0
0
0
0
0
0
R = Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 1 of 11)
M68HC11K Family
MOTOROLA
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Technical Data
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