M68HC11K_13 Datasheet, PDF (115/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
5.4 Effects of Reset
When the MCU recognizes a reset condition, it forces the CPU registers
and control bits to established initial states. These in turn force the
on-chip peripheral systems to known startup states, as described here.
• Central processor unit (CPU)
– The stack pointer and other CPU registers are indeterminate
immediately after reset, except for three bits in the condition
code register (CCR).
– The X and I interrupt mask bits are set to mask any interrupt
requests, and the S bit in the CCR is set to inhibit the stop
mode.
• Memory map
– The INIT register is initialized to $00, putting the control
registers at locations $0000–$007F.
– The 1.5 Kbytes of RAM are at locations $0080–$067F except
for the M68HC11KS Family, which has 1 Kbytes of RAM at
locations $0080–$047F.
– The INIT2 register is $00, locating the EEPROM at
$0D80–$0FFF.
• Timer
– The timing system is initialized to a count of $0000.
– The prescaler bits are cleared, and all output compare
registers are initialized to $FFFF.
– All input capture registers are indeterminate after reset.
– The output compare 1 mask (OC1M) register is cleared so that
successful OC1 compares do not affect any input/output (I/O)
pins. The other four output compares are configured so that
they do not affect any I/O pins on successful compares.
– All input capture edge-detector circuits are configured for
capture disabled operation.
– The timer overflow interrupt flag and all eight timer function
interrupt flags are cleared.
M68HC11K Family
MOTOROLA
Resets and Interrupts
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Technical Data
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