M68HC11K_13 Datasheet, PDF (208/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Timing System
Freescale Semiconductor, Inc.
9.7.5 Pulse Accumulator Count Register
Address: $0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 9-26. Pulse Accumulator Count Register (PACNT)
In event counting mode, PACNT contains the count of external input
events at the PAI input. In gated accumulation mode, PACNT is
incremented by the pulse accumulator’s E ÷ 64 clock when the PAI input
is at the selected level. Counting is synchronized to the internal PH2
clock so that incrementing and reading occur during opposite half cycles.
The counter is not affected by reset and can be read or written to at any
time.
9.8 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) feature generates hardware interrupts at a
fixed periodic rate. The rate is determined by bits RTR[1:0] in the PACTL
register, which further divide a clock running at E ÷ 2¹³ by 1, 2, 4 or 8.
The resulting periods for various common crystal frequencies are shown
in Table 9-7.
Every cycle of the RTI clock sets the RTIF bit in timer interrupt flag 2
(TFLG2) register. This flag can be polled to determine when RTI
timeouts occur, or an interrupt can be generated if the RTII bit in the
timer interrupt mask 2 (TMSK2) register is set. After reset, one entire
real-time interrupt period elapses before the RTIF flag is set for the first
time.
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. The time between successive
RTI timeouts is a constant that is independent of software latencies
Technical Data
208
Timing System
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M68HC11K Family
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