M68HC11K_13 Datasheet, PDF (146/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Freescale Semiconductor, Inc.
Parallel Input/Output
6.10 Port H
The state of port H pin 7 (PH7) at reset is mode dependent. In single-chip
or bootstrap modes, it is a high-impedance input; its data direction can
be changed through DDRH. In expanded and special test modes PH7 is
the program chip select line, CSPROG at reset, but can be reconfigured
for GPIO (see 11.4 Chip Selects).
Port H pins (PH[6:0]) reset to high-impedance inputs in any mode. Data
direction can be changed through DDRH. Except for the M68HC11KS
devices, bits 6:4 can serve as chip select lines in expanded and special
test modes (see 11.4 Chip Selects). Pins 3:0 can be configured as
pulse-width modulator outputs (see 9.9 Pulse-Width Modulator
(PWM)) in any mode.
All eight port H pins have selectable internal pullup resistors (see
6.11 Internal Pullup Resistors).
Address: $007C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PH7⁽¹⁾ PH6⁽¹⁾ PH5⁽¹⁾ PH4⁽¹⁾
PH3
PH2
PH1
PH0
Write:
Reset: 0
0
0
0
0
0
0
0
Alternate Pin Function: CSPROG CSPG2 CSPG1 CSIO PW4
PS3
PS2
PS1
1. Not available on KS devices
Figure 6-15. Port H Data Register (PORTH)
Address: $007D
Bit 7
6
5
4
3
2
1
Read:
DDH7⁽¹⁾ DDH6⁽¹⁾ DDH5⁽¹⁾ DDH4⁽¹⁾
Write:
DDH3
DDH2
DDH1
Reset: 0
0
0
0
0
0
0
1. Not available on KS devices
Figure 6-16. Port H Data Direction Register (DDRH)
DDH[7:0] — Data Direction for Port H Bits
0 = Input
1 = Output
Bit 0
DDH0
0
Technical Data
146
Parallel Input/Output
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M68HC11K Family
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