M68HC11K_13 Datasheet, PDF (136/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Freescale Semiconductor, Inc.
Parallel Input/Output
6.2 Introduction
The M68HC11K series MCUs contain eight input/output (I/O) ports, A
through H. All ports can provide general-purpose I/O (GPIO) as well as
their specialized functions, as explained in 2.11 Port Signals and
summarized in Table 6-1.
Table 6-1. Port Configuration
Port
Input Output
Pins
Pins
Bidirectional
Pins
Shared Functions
Port A
—
—
8
Timer
Port B
—
—
8
High-order address
Port C —
—
8
Data bus
Port D —
—
6
SCI and SPI
Port E
8
—
—
A/D converter
Port F
—
—
8
Low-order address
Port G —
—
8⁽¹⁾
Memory expansion
Port H —
—
8⁽²⁾
Chip selects and PWM
1. KS devices do not contain port G[6:0], so they have only one bidirectional pin on this port.
2. KS devices do not contain port H[7:4], so they have only four bidirectional pins on this port.
Each of the ports has an associated data register (PORTx). Each port,
except port E, also has an associated data direction register (DDRx).
When a port is configured for GPIO, its DDR determines whether port
pins function as inputs or outputs. A port’s special functions override the
DDR when they are enabled.
Writes to any port, except port E, are stored in internal latches. The
latches drive the port pins only when they are configured as
general-purpose outputs.
When software reads a port pin configured for GPIO, the MCU returns
the physical pin level, not the port register value. This applies to both
inputs and outputs. The only exception applies to ports C and D in
wired-OR mode. When they are configured as outputs, a read returns
the pin driver levels.
Technical Data
136
Parallel Input/Output
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M68HC11K Family
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