M68HC11K_13 Datasheet, PDF (122/290 Pages) Freescale Semiconductor, Inc – M68HC11K Family Technical Data

Freescale Semiconductor, Inc.
Resets and Interrupts
5.6 Reset and Interrupt Priority
A hardware priority scheme determines which reset or interrupt is
serviced first when simultaneous requests occur.
The six highest-priority interrupt sources are not maskable. The priority
arrangement for these sources is:
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
The maskable interrupt sources have this priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system
Technical Data
122
Resets and Interrupts
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M68HC11K Family
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