K10P81M72SF1 Datasheet, PDF (65/73 Pages) Freescale Semiconductor, Inc – K10 Sub-Family

Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
81 80
MAP LQFP
BGA
Pin Name
E4 1 PTE0
E3 2 PTE1/
LLWU_P0
E2 3 PTE2/
LLWU_P1
F4 4 PTE3
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ALT0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ALT1
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
E7 — VDD
F7 — VSS
H7 5 PTE4/
LLWU_P2
G4 6 PTE5
E6 7 VDD
G7 8 VSS
F1 9 PTE16
F2 10 PTE17
VDD
VSS
DISABLED
DISABLED
VDD
VSS
ADC0_SE4a
ADC0_SE5a
VDD
VSS
VDD
VSS
ADC0_SE4a
ADC0_SE5a
PTE4/
LLWU_P2
PTE5
PTE16
PTE17
ALT2
ALT3
ALT4
SPI1_PCS1 UART1_TX
SPI1_SOUT UART1_RX
SPI1_SCK
SPI1_SIN
UART1_CTS_
b
UART1_RTS_
b
SPI1_PCS0 UART3_TX
SPI1_PCS2 UART3_RX
SPI0_PCS0 UART2_TX FTM_CLKIN0
SPI0_SCK UART2_RX FTM_CLKIN1
G1 11 PTE18
ADC0_SE6a ADC0_SE6a PTE18
G2 12 PTE19
ADC0_SE7a ADC0_SE7a PTE19
L6 — VSS
VSS
VSS
K1 13 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
K2 14 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
L1 15 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
L2 16 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
F5 17 VDDA
VDDA
VDDA
G5 18 VREFH
VREFH
VREFH
G6 19 VREFL
VREFL
VREFL
F6 20 VSSA
VSSA
VSSA
SPI0_SOUT
SPI0_SIN
UART2_CTS_ I2C0_SDA
b
UART2_RTS_ I2C0_SCL
b
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
FTM0_FLT3
LPTMR0_
ALT3
K10 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
65