K10P81M72SF1 Datasheet, PDF (57/73 Pages) Freescale Semiconductor, Inc – K10 Sub-Family

Peripheral operating requirements and behaviors
6.8.3 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 39. Master mode DSPI timing (full voltage range)
Num
DS1
DS2
DS3
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DS4
DSPI_SCK to DSPI_PCSn invalid delay
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
Min.
1.71
—
4 x t_BUS
(t_SCK/2) - 4
(t_BUS x 2) −
4
(t_BUS x 2) −
4
—
-4.5
20.5
0
Max.
3.6
12.5
—
(t_SCK/2) + 4
—
—
10
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
3
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS2
DS1
DS4
DS7
DS8
First data
DS5
First data
Data
Last data
DS6
Data
Last data
Figure 23. DSPI classic SPI timing — master mode
K10 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
57