MC9S08DE60 Datasheet, PDF (59/412 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
corresponding high-page control registers at reset. There is also an 8-byte comparison key in Flash
memory. Refer to Table 4-3 and Table 4-5 for the absolute address assignments for all Flash and EEPROM
registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
4.5.12.1 Flash and EEPROM Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
7
6
5
4
3
2
1
0
R DIVLD
PRDIV8
DIV
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-5. Flash and EEPROM Clock Divider Register (FCDIV)
Table 4-7. FCDIV Register Field Descriptions
Field
7
DIVLD
6
PRDIV8
5:0
DIV
Description
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for Flash and EEPROM.
Prescale (Divide) Flash and EEPROM Clock by 8 (This bit is write once.)
0 Clock input to the Flash and EEPROM clock divider is the bus rate clock.
1 Clock input to the Flash and EEPROM clock divider is the bus rate clock divided by 8.
Divisor for Flash and EEPROM Clock Divider — These bits are write once. The Flash and EEPROM clock
divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV
field plus one. The resulting frequency of the internal Flash and EEPROM clock must fall within the range of
200 kHz to 150 kHz for proper Flash and EEPROM operations. Program/Erase timing pulses are one cycle of
this internal Flash and EEPROM clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1 and Equation 4-2.
if PRDIV8 = 0 — f_FCLK = f_Bus ÷ (DIV + 1)
if PRDIV8 = 1 — f_FCLK = f_Bus ÷ (8 × (DIV + 1))
Table 4-8 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
Eqn. 4-1
Eqn. 4-2
MC9S08DE60 Series Data Sheet, Rev. 3
Freescale Semiconductor
59