MC9S08DE60 Datasheet, PDF (58/412 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
4.5.10 Error Correction Code
The Flash memory includes error correction code (ECC) logic that implements Hamming code to correct
single bit faults during all Flash array read operations. ECC is an optional feature that can be enabled by
programming the NVECC configuration byte, such that upon the next reset, the ECCDIS configuration bit
will read zero and thus enabling ECC.
4.5.10.1 Enable ECC
Fully erased parts default to ECC disabled for main reads and programs (NVECC = 0xFF). To enable ECC
in user mode, users need to program NVECC to 0x66, then pull a reset to execute the reset sequence that
would clear ECCDIS. The ECC parity code for 0x66 is 0xF so if users ever read the NVECC location after
ECC is turned on, they will get a valid ECC result even though the original byte was programmed with
ECC off. When NVECC is read during the reset sequence with ECC off, if either nibble of NVECC is 0x6,
then ECC is enabled. Even though the parity bits are ignored, a single bit fault will not prevent a
programmed NVECC from enabling ECC and a single bit fault will not prevent an erased NVECC from
disabling ECC. The ECCDIS bit will be based on the contents of NVECC read during the reset sequence.
When a part is first programmed through the background debug controller, the programmer is able to write
to the ECCDIS bit to enable ECC if desired and then program the entire S-record file including NVECC.
4.5.10.2 ECC Remapping
The ECC logic implements a single-bit correction method which stores four parity bits per eight data bit.
The array architecture of the Flash allows for one third of the code storage bits to be used as ECC parity
bits when ECC is turned on. The Flash sector size becomes 512 bytes when ECC is enabled and the entire
array is remapped yielding a continuous address range across sectors.
4.5.11 EEPROM Mapping
Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half
of the array can be accessed in foreground while the other half can not be accessed in background. There
are two mapping mode options that can be selected to configure the 8-byte EEPROM sectors: 4-byte mode
and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register.
In 4-byte sector mode (EPGMOD = 0), each 8-byte sector splits four bytes on foreground and four bytes
on background but on the same addresses. The EPGSEL bit selects which four bytes can be accessed.
During a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is
erased.
In 8-byte sector mode (EPGMOD = 1), each entire 8-byte sector is in a single page. The EPGSEL bit
selects which sectors are on background. During a sector erase, the entire 8-byte sector in foreground is
erased.
4.5.12 Flash and EEPROM Registers and Control Bits
The Flash and EEPROM modules have seven 8-bit registers in the high-page register space and three
locations in the nonvolatile register space in Flash memory. Two of those locations are copied into two
MC9S08DE60 Series Data Sheet, Rev. 3
58
Freescale Semiconductor