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MC9S08DE60 Datasheet, PDF (239/412 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
12.3.14 MSCAN Transmit Error Counter (CANTXERR)
This register reï¬ects the status of the MSCAN transmit error counter.
R
W
Reset:
7
TXERR7
0
6
TXERR6
5
TXERR5
0
0
= Unimplemented
4
TXERR4
0
3
TXERR3
0
2
TXERR2
0
1
TXERR1
0
0
TXERR0
0
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
12.3.15 MSCAN Identiï¬er Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identiï¬er acceptance and identiï¬er mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0âIDR3 registers (see Section 12.4.1,
âIdentiï¬er Registers (IDR0âIDR3)â) of incoming messages in a bit by bit manner (see Section 12.5.3,
âIdentiï¬er Acceptance Filterâ).
For extended identiï¬ers, all four acceptance and mask registers are applied. For standard identiï¬ers, only
the ï¬rst two (CANIDAR0/1, CANIDMR0/1) are applied.
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 12-19. MSCAN Identiï¬er Acceptance Registers (First Bank) â CANIDAR0âCANIDAR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S08DE60 Series Data Sheet, Rev. 3
Freescale Semiconductor
239
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