MC68HC05RC8 Datasheet, PDF (59/122 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Input/Output Programming
the ports to inputs. Writing a one to a DDR bit sets the corresponding
port bit to output mode. Port C pins PC4–PC7 are available only with the
44-lead PLCC package.
NOTE:
Only four bits of port C are bonded out in 28-pin packages for the
MC68HC05RC16, although port C is truly an 8-bit port. Since pins
PC4–PC7 are unbonded, software should include the code to set their
respective data direction register locations to outputs to avoid floating
inputs.
7.6 Input/Output Programming
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
Access
Write
Write
Read
Read
DDR
0
1
0
1
Table 7-1. I/O Pin Functions
I/O Pin Functions
The I/O pin is in input mode. Data is written into the output
data latch.
Data is written into the output data latch and output to the
I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.
MC68HC05RC16 — Rev. 3.0
General Release Specification
Parallel Input/Output (I/O)
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