MC68HC05RC8 Datasheet, PDF(47/122 Page) Freescale Semiconductor, Inc

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MC68HC05RC8 Datasheet, PDF (47/122 Pages) Freescale Semiconductor, Inc – General Release Specification

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VDD

OSC12

INTERNAL

PROCESSOR

CLOCK1

INTERNAL

ADDRESS

BUS1

INTERNAL

DATA

BUS1

4064 tCYC

tCYC

3FFE 3FFF NEW PC NEW PC

NEW NEW

PCH PCL

CODE

RESET5

> VPOR 4

3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC

PCH PCL

CODE

tRL

NOTES:

1. Internal timing signal and bus information are not available externally.

2. OSC1 line is not meant to represent frequency. It is only used to represent time.

3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset.

5. The LPRST pin resets the CPU like RESET. However, 4064 POR cycles are executed first, before the reset vector address appears on the

internal address bus. (See 5.4 Low-Power External Reset (LPRST).)

Figure 5-2. Reset and POR Timing Diagram

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